(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming field isolation.
(2) Description of Prior Art
The formation of integrated circuit devices on silicon substrates requires that a means be provided to electrically isolate the various circuit components from each other. To this end regions of field insulation, typically of silicon oxide, are formed adjacent to the circuit components.
The well known method of local oxidation of silicon(LOCOS) to form field oxide isolation around semiconductive devices built into the surface of silicon wafers has been practiced for over twenty-five years and has served well to provide field isolation for many applications. Over the years many problems with LOCOS have surfaced which have been addressed in a great variety of ways. Most notable are the problems which deal with the growth of oxide under the hardmask used to define the oxide regions and the resultant uneven surface topology over the field oxide. The oxide penetration under the mask is commonly referred to as birdsbeak. These problems still persist and become aggravated as the technology tends towards smaller, shallower devices at high densities.
A promising replacement for LOCOS field oxide isolation has been found in trench isolation. Although deep trench isolation(DTI) has been used nearly as long as LOCOS for bipolar transistor isolation, it has not been widely practiced in the manufacture of CMOS (complimentary metal oxide silicon) integrated circuits. More recently, however, as device densities increase and isolation widths become smaller, shallow trench isolation(STI) is gaining favor over LOCOS in CMOS technology. The Trenches are formed in the silicon around the semiconductor devices by reactive ion etching. They are then filled either entirely with silicon oxide or lined with thermal silicon oxide and filled with another material such as polysilicon. The thin (&lt;200 .ANG.) thermal silicon oxide liner is included even when the trench filler material is an insulator.
Unlike LOCOS field isolation, the geometric features of STI are generally more abrupt, presenting sharp corners at both the top and bottom of the trenches. The sharp features, although welcomed by the smaller and denser circuit designs, aggravate device performance issues which are stress related. In particular, major problems are encountered when STI is used in CMOS technology that are caused by electric field crowding at the edges of the active device regions. These problems include anomalous sub-threshold conduction and poor gate oxide integrity. In addition, tensile stresses are induced in the devices themselves by shrinkage of the trench filling oxide through densification of the oxide during subsequent annealing.
A recent innovation in STI technology has been the incorporation of a silicon nitride liner over the thin thermal silicon oxide liner. The silicon nitride liner acts as an oxidation barrier during a pyrogenic oxide anneal which enables improved densification of the filler oxide. Such a technique was introduced by Fahey, et.al. U.S. Pat. No. 5,447,884 wherein a silicon nitride liner less than 5 nm. thick was deposited over the thermal oxide. A pyrogenic anneal(wet oxidation conditions) permitted densification of the oxide filler at lower temperatures than the conventional argon anneal. In addition the wet oxidation step removed fluorine which was not the case with an argon anneal. Ho, et.al., U.S. Pat. No. 5,643,823 crystallized the amorphous as deposited silicon nitride liners by rapid thermal anneal (RTA), thereby permitting the use of thicker silicon nitride liners without incurring undercutting by wet etches which are used to remove a pad nitride layer used as the RIE(reactive ion etching) hardmask for etching the silicon trench. Bose, et.al., U.S. Pat. No. 5,492,858 also introduced a silicon nitride liner in an STI process wherein the liner served not only as an oxidation barrier during steam densification of the filler oxide, but also provided a more receptive surface than the thermal oxide to form a more durable bond with the conformal dielectric filler material.
After the filler oxide has been deposited and densified by pyrogenic annealing as taught by the prior art, the silicon nitride hardmask used for the trench RIE and the accompanying pad oxide are removed by wet etching, leaving a structure which is shown in a cross section of the wafer 10 in FIG. 1. The trench 20 has been filled with LPCVD silicon oxide and densified by annealing. The pad oxide 12 and the silicon nitride liner 14 remain under the filler oxide 16. Also shown in FIG. 1 is a slight undercut of the pad oxide adjacent to the sharp upper silicon corner 18, which is likely to occur since the pad oxide is removed a wet etch.
The sharp corner 18, which is not addressed by the prior art, is conventionally ignored and a gate oxide 22 is grown over the exposed silicon active area. The gate oxide thus formed is thinner at the sharp corner 18 than over the planar region. This creates a gate oxide integrity risk along the edges of the active channel region. In addition, the tensile stresses in the densified filler oxide extend stresses into the channel region, thereby causing crystalline distortions and defects in the channel region which result in anomalous currents and leakages in subsequently formed MOSFETs.
Paoli, et.al., U.S. Pat. No. 5,641,704 shows a method for forming STI using trench liners and planarization but does not address problems related to the abrupt corners at the edges of channel regions of MOSFETs encountered in the process.
The application of spacers along the edge of the filler oxide may be used to offset the edge of the channel region from the sharp corner, however, the dimensions of these spacers would be comparable with the widths of narrow channel devices and would consequently reduce the drive current capabilities of these devices.